View ISL97672IRZ_4951424.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

6-Channel LED Driver
ISL97672
The ISL97672 is an integrated power LED driver that controls 6 channels of LED current for LCD backlight applications. The ISL97672 is capable of driving up to 78 LEDs from 4.5V to 26V or 48 LEDs from a boost supply of 2.7V to 26V and a separate 5V bias supply on the VIN pin. The ISL97672 compensates for non-uniformity of the forward voltage drops in the LED strings with its 6 voltage controlled-current source channels. Its headroom control monitors the highest LED forward voltage string for output regulation, to minimize the voltage headroom and power loss in a typical multi-string operation. The ISL97672 allows direct PWM mode by following the external signal from 0Hz to 30KHz at 0.4% to 100% duty cycle and maintaining a typical 0.7% current matching between channels. The ISL97672 features a separate EN pin and extensive protection functions that flag whenever a fault occurs. The protections include string open and short circuit detections, OVP, OTP, thermal shutdown and an optional input overcurrent protection with fault disconnect switch.
ISL97672
Features
* 6 Channels * 4.5V to 26.5V Input * 45V Output Max * Up to 40mA LED Current per channel * Direct PWM Dimming without Phase Shift * PWM Dimming Linearity 0.4%~100% <30kHz * Adjustable 200kHz to 1.4MHz Switching Frequency * Dynamic Headroom Control * Protections with Flag Indication - String Open/Short Circuit, VOUT Short Circuit, Overvoltage and Over-Temperature Protections - Optional Master Fault Protection * Current Matching 0.7% * 20 Ld 4mmx3mm QFN Package
Applications*(see page 16)
* Notebook Displays LED Backlighting * LCD Monitor LED Backlighting * Automotive Displays LED Backlighting * Automotive or Traffic Lighting
Related Literature*(see page 16)
* See AN1581, "ISL97671/2/3/4IRZ-EVAL Quick Start Guide"
Typical Application Circuit
VIN = 4.5V~26.5V VOUT = 45V*, 40mA PER STRING
ISL97672 1 FAULT 2 VIN 4 VDC 18 COMP 6 /FLAG CH0 10 CH1 11 5 PWM 3 EN 17 RSET 8 FSW 9 AGND CH2 12 CH3 13 CH4 14 CH5 15 LX 20 OVP 16
PGND 19
* VIN > 12V
FIGURE 1. ISL97672 TYPICAL APPLICATION DIAGRAM
November 1, 2010 FN7632.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774| Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. Copyright Intersil Americas Inc. 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL97672
Block Diagram
VIN = 4.5V~26V
(Optional Q1) VIN EN VDC FAULT Bias fsw
Fault Flag
45V*,40mA per string 25mA 78 (6x13) LEDs
10uH/3A LX 4.7uF/50V
REG OSC & RAMP Comp
O/P Short OVP
Boost SW
OVP
/FLAG
Fault Flag
=0
Imax
ILIMIT
Logic
FET Driver
PGND
Fault/Status Control
COMP
GM AMP
VSET
Open Ckt, Short Ckt Detects
p e
Highest VF String Detect
+ -
CH0 CH1 CH5
0
RSET
+ -
REF GEN
REF_VSC
Temp Sensor
Fault Flag
PWM0
1
GND
REF_OVP
+ -
PWM1
PWM
PWM GENERATOR
PWM5
VVin >6V * IN > 12V
+ -
5
ISL97672
FIGURE 2. ISL97672 BLOCK DIAGRAM
2
FN7632.1 November 1, 2010
ISL97672
Ordering Information
PART NUMBER (Notes 1, 2, 3) ISL97672IRZ PART MARKING 7672 PACKAGE (Pb-Free) 20 Ld 4x3 QFN PKG. DWG. # L20.3x4
Pin Configuration
ISL97672 (20 LD 4X3 QFN) TOP VIEW
COMP 18 PGND RSET 17 16 OVP 15 CH5 14 CH4 13 CH3 12 CH2 11 CH1 7 NC 8 FSW 9 AGND 10 CH0 LX 20 FAULT VIN EN VDC PWM /FLAG 1 2 3 4 5 6
ISL97672IRZ-EVAL Evaluation Board NOTES: 1. Add "-T" or "-TK" suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL97672. For more information on MSL please see techbrief TB363.
19
Pin Descriptions
PIN NAME FAULT VIN EN VDC PWM /FLAG NC FSW AGND CH0 CH1 CH2 CH3 CH4 CH5 OVP RSET COMP PGND LX PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 TYPE O S I S I O I I S I I I I I I I I O S O
(I = Input, O = Output, S = Supply)
DESCRIPTION
Fault disconnect switch Input voltage for the device and LED power The device needs 4ms for initial power-up Enable. It will be disabled if it is not biased for longer than 28ms. De-couple capacitor for internally generated supply rail. PWM brightness control pin. /Flag = 0 for any fault conditions. /Flag =1 for normal condition. Open drain that needs pull up. No Connect Boost switching frequency set pin by connecting a resistor. See "Switching Frequency" on page 10 for resistor calculation Analog Ground for precision circuits Input 0 to current source, FB, and monitoring Input 1 to current source, FB, and monitoring Input 2 to current source, FB, and monitoring Input 3 to current source, FB, and monitoring Input 4 to current source, FB, and monitoring Input 5 to current source, FB, and monitoring Overvoltage protection input Resistor connection for setting LED current, (see Equation 1 for calculating the ILEDpeak) Boost compensation pin Power ground (LX Power return) Input to boost switch
3
FN7632.1 November 1, 2010
ISL97672
Absolute Maximum Ratings (TA = +25C)
VIN, EN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 28V FAULT . . . . . . . . . . . . . . . . . . . . . VIN - 8.5V to VIN + 0.3V VDC, COMP, RSET, PWM, OVP, /FLAG, FSW . . . -0.3V to 5.5V CH0 - CH5, LX . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 45V PGND, AGND . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V Above voltage ratings are all with respect to AGND pin ESD Rating Human Body Model (Tested per JESD22-A114E) . . . . . 3kV Machine Model (Tested per JESD22-A115-A) . . . . . . . 300V Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . 1kV Latch Up (Tested per JESD-78B; Class 2, Level A) . . . 100mA
Thermal Information
Thermal Resistance (Typical) 20 Ld QFN Package (Notes 4, 5, 7) . Thermal Characterization (Typical) JA (C/W) JC (C/W) 40 2.5 PSIJT (C/W)
20 Ld QFN Package (Note 6) . . . . . . . . . . . . 1 Absolute Maximum Junction Temperature . . . . . . . . +150C Recommended Max Operating Junction Temperature . +125C Storage Temperature . . . . . . . . . . . . . . . -65C to +150C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . -40C to +85C
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 5. For JC, the "case temp" location is the center of the exposed metal pad on the package underside assumed under ideal case temperature. 6. PSIJT is the junction-to-top thermal resistance. If the package top temperature can be measured, with this rating then the die junction temperature can be estimated more accurately than the JC and JC thermal resistance ratings. 7. Refer to JESD51-7 high effective thermal conductivity board layout for proper via and plane designs.
Electrical Specifications
All specifications below are tested at TA = +25C; VIN = 12V, EN = 5V, RSET = 20.1k, unless otherwise noted. Boldface limits apply over the operating temperature range, -40C to +85C. CONDITION MIN (Note 8) TYP MAX (Note 8) UNIT
PARAMETER GENERAL VIN (Note 9) IVIN_STBY VOUT
DESCRIPTION
Backlight Supply Voltage VIN Shutdown Current Output Voltage
TC = <+60C TA = +25C
4.5
26.5 10
V A V V V V mV
4.5V < VIN 26V, FSW = 600kHz 8.55V < VIN 26V, FSW = 1.2MHz 4.5V < VIN 8.55V, FSW = 1.2MHz
45 45 VIN/0.19 2.6 275 3.3
Vuvlo Vuvlo_hys
Undervoltage Lock-out Threshold Undervoltage Lock-out Hysteresis
ENABLE AND PWM GENERATOR VIL VIH FPWM tON Guaranteed Range for PWM Input Low Voltage Guaranteed Range for PWM Input High Voltage PWM Input Frequency Range Minimum On Time 1.5 200 250 0.8 VDD 30,000 350 V V Hz ns
4
FN7632.1 November 1, 2010
ISL97672
Electrical Specifications
All specifications below are tested at TA = +25C; VIN = 12V, EN = 5V, RSET = 20.1k, unless otherwise noted. Boldface limits apply over the operating temperature range, -40C to +85C. (Continued) CONDITION MIN (Note 8) TYP MAX (Note 8) UNIT
PARAMETER REGULATOR VDC IVDC_STBY IVDC VLDO ENLow ENHi tENLow BOOST SWILimit rDS(ON) SS Eff_peak
DESCRIPTION
LDO Output Voltage Standby Current Active Current VDC LDO Droop Voltage Guaranteed Range for EN Input Low Voltage Guaranteed Range for EN Input High Voltage EN low time before shut-down
VIN > 6V EN = 0V EN = 5V VIN > 5.5V, 20mA
4.55
4.8
5 5
V A mA
5 20 200 0.5 1.8 30.5
mV V V ms
Boost FET Current Limit Internal Boost Switch ON-Resistance Soft-start Peak Efficiency TA = +25C 100% LED Duty Cycle VIN = 12V, 72 LEDs, 20mA each, L = 10H with DCR 101m, TA = +25C VIN = 12V, 60 LEDs, 20mA each, L = 10H with DCR 101m, TA = +25C
1.5
2.0 235 7 92.9
2.7 300
A m ms %
90.8
%
IOUT/VIN Dmax
Line Regulation Boost Maximum Duty Cycle FSW = 600kHz FSW = 1.2MHz 90 81
0.1
% % % 9.5 17 % % kHz MHz A
Dmin
Boost Minimum Duty Cycle
FSW = 600kHz FSW = 1.2MHz
fS fS ILX_leakage
Minimum Switching Frequency Maximum Switching Frequency LX Leakage Current
RFSW = 200k RFSW = 33k LX = 45V, EN = 0
175 1.312
200 1.50
235 1.69 10
CURRENT SOURCES IMATCH IACC Vheadroom VRSET ILEDmax Channel-to-Channel Current Matching Current Accuracy Dominant Channel Current Source Headroom at IIN Pin Voltage at RSET Pin Maximum LED Current per Channel ILED = 20mA TA = +25C RSET = 20.1k VIN = 12V, VOUT = 45V, Fsw = 1.2MHz, TA = +25C 1.2 RSET =20.1k (IOUT = 20mA) -1.5 500 1.22 40 1.24 0.7 1.0 +1.5 % % mV mV mA
FAULT DETECTION VSC Temp_shtdwn Temp_Hyst Short Circuit Threshold Temperature Shutdown Threshold Temperature Shutdown Hysteresis PWM Dimming = 100% 5.2 5.85 150 23 6.6 V C C
5
FN7632.1 November 1, 2010
ISL97672
Electrical Specifications
All specifications below are tested at TA = +25C; VIN = 12V, EN = 5V, RSET = 20.1k, unless otherwise noted. Boldface limits apply over the operating temperature range, -40C to +85C. (Continued) CONDITION MIN (Note 8) 1.19 400 When Fault Occurs 0.4 TYP MAX (Note 8) UNIT 1.25 V mV V
PARAMETER VOVPlo OVPfault FLAG_ON FAULT PIN IFAULT VFAULT LXstart_thres ILXStartup NOTES:
DESCRIPTION Overvoltage Limit on OVP Pin OVP Short Detection Fault Level Fault Flag
Fault Pull-down Current Fault Clamp Voltage with Respect to VIN LX Start-up Threshold LX Start-up Current
VIN = 12V VIN = 12, VIN-VFAULT
12 6 1.3
21 7 1.4 3.5
30 8.3 1.5 5
A V V mA
VDC = 5.0V
1
8. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 9. At maximum VIN of 26.5VV, minimum VOUT is 28V. Minimum VOUT can be lower at lower VIN. 10. Limits established by characterization and are not production tested.
Typical Performance Curves
100 90 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0 5 10 15 20 25 EFFICIENCY (%) 80 12VIN 24VIN 5VIN 100 90 80 70 60 50 40 30 20 10 0 0 5 10 15 20 ILED(mA) 25 30 35 12VIN 24VIN 5VIN 6P10S_30mA/CHANNEL
ILED(mA)
FIGURE 3. EFFICIENCY vs up to 20mA LED CURRENT (100% LED DUTY CYCLE) vs VIN
FIGURE 4. EFFICIENCY vs up to 30mA LED CURRENT (100% LED DUTY CYCLE) vs VIN
100 90 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0 5 10 15 VIN 20 25 30 EFFICIENCY (%) 80 580k 1.2MHz
100 80 60 40 20 0 0 580k 1.2MHz
5
10
15 VIN
20
25
30
FIGURE 5. EFFICIENCY vs VIN vs SWITCHING FREQUENCY AT 20mA (100% LED DUTY CYCLE)
FIGURE 6. EFFICIENCY vs VIN vs SWITCHING FREQUENCY AT 30mA (100% LED DUTY CYCLE)
6
FN7632.1 November 1, 2010
ISL97672
Typical Performance Curves
100 80 EFFICIENCY (%) 70 +25C 60 50 40 30 20 10 0 0 5 10 15 VIN 20 25 +85C 0C -40C 90
(Continued)
0.40 CURRENT MATCHING(%) 0.30 0.20 0.10 0.00 -0.10 -0.20 -0.30 -0.40 0 1 2 3 21 VIN 4 5 6 7 4.5 VIN
12 VIN
30
CHANNEL
FIGURE 7. EFFICIENCY vs VIN vs TEMPERATURE AT 20mA (100% LED DUTY CYCLE)
FIGURE 8. CHANNEL-TO-CHANNEL CURRENT MATCHING
1.2 1.0 0.8 0.6 0.4 0.2 0 VHEADROOM (V)
0.60 +25C 0.55 -40C
CURRENT
4.5 VIN 12 VIN
0.50
0C
0.45
0
1
2
3 DC
4
5
6
0.40 0
5
10
15 VIN (V)
20
25
30
FIGURE 9. CURRENT LINEARITY vs LOW LEVEL PWM DIMMING DUTY CYCLE vs VIN
FIGURE 10. VHEADROOM vs VIN AT 20mA
FIGURE 11. VOUT RIPPLE VOLTAGE, VIN = 12V, 6P12S AT 20mA/CHANNEL
FIGURE 12. IN-RUSH and LED CURRENT AT VIN = 6V FOR 6P12S AT 20mA/CHANNEL
7
FN7632.1 November 1, 2010
ISL97672
Typical Performance Curves
(Continued)
FIGURE 13. IN-RUSH AND LED CURRENT AT VIN = 12V FOR 6P12S AT 20mA/CHANNEL
FIGURE 14. LINE REGULATION WITH VIN CHANGE FROM 6V TO 26V, VIN = 12V, 6P12S AT 20mA/CHANNEL
FIGURE 15. LINE REGULATION WITH VIN CHANGE FROM 26V TO 6V FOR 6P12S AT 20mA/CHANNEL
FIGURE 16. LOAD REGULATION WITH ILED CHANGE FROM 0% TO 100% PWM DIMMING, VIN = 12V, 6P12S AT 20mA/CHANNEL
FIGURE 17. LOAD REGULATION WITH ILED CHANGE FROM 100% TO 0% PWM DIMMING, VIN = 12V, 6P12S AT 20mA/CHANNEL
FIGURE 18. ISL97671 SHUTS DOWN AND STOPS SWITCHING ~ 30ms AFTER EN GOES LOW
8
FN7632.1 November 1, 2010
ISL97672
Theory of Operation
PWM Boost Converter
The current mode PWM boost converter produces the minimal voltage needed to enable the LED stack with the highest forward voltage drop to run at the programmed current. The ISL97672 employs current mode control boost architecture that has a fast current sense loop and a slow voltage feedback loop. Such architecture achieves a fast transient response that is essential for the notebook backlight application where the power can be a series of drained batteries or instantly changed to an AC/DC adapter without rendering a noticeable visual nuisance. The number of LEDs that can be driven by ISL97672 depends on the type of LED chosen in the application. The ISL97672 is capable of boosting up to 45V and typically driving 13 LEDs in series for each of the 8 channels, enabling a total of 104 pieces of the 3.2V/20mA type of LEDs.
+ RSET
REF
+ -
+ PWM DIMMING
FIGURE 19. SIMPLIFIED CURRENT SOURCE CIRCUIT
Enable
The Enable pin is used to enable the device. If there is no signal for longer than 28ms, the device will enter shutdown. Do not let Enable pin floating thus a 10k or higher pull-down resistor should be added.
OVP and VOUT
The Over Voltage Protection (OVP) pin has a function of setting the overvoltage trip level as well as limiting the VOUT regulation range. The ISL97672 OVP threshold is set by RUPPER and RLOWER such that: VOUT_ovp = 1.21V*(RUPPER+RLOWER)/RLOWER and VOUT can only regulate between 61% and 100% of the VOUT_ovp such that: Allowable VOUT = 61% to 100% of VOUT_ovp For example, if 10 LEDs are used with the worst case VOUT of 35V. If R1 and R2 are chosen such that the OVP level is set at 40V, then the VOUT is allowed to operate between 24.4V and 40V. If the requirement is changed to a 6 LEDs of 21V VOUT application, then the OVP level must be reduced and users should follow VOUT = (61% ~100%) OVP level requirement. Otherwise, the headroom control will be disturbed such that the channel voltage can be much higher than expected and sometimes it can prevent the driver from operating properly. The ratio of the OVP capacitors should be the inverse of the OVP resistors. For example, if RUPPER/RLOWER = 33/1, then CUPPER/CLOWER = 1/33 with CUPPER = 100pF and CLOWER = 3.3nF.
The source terminals of the current source MOSFETs are designed to run at 500mV to optimize power loss versus accuracy requirements. The sources of errors of the channel-to-channel current matching come from the op amp's offset, internal layout and reference and these parameters are optimized for current matching and absolute current accuracy. The absolute accuracy is also determined by the external RSET. A 1% tolerance resistor should be used.
Dynamic Headroom Control
The ISL97672 features a proprietary Dynamic Headroom Control circuit that detects the highest forward voltage string or effectively the lowest voltage from any of the CH0-CH5 pins. When this lowest channel voltage is lower than the short circuit threshold, VSC, such voltage will be used as the feedback signal for the boost regulator. The boost makes the output to the correct level such that the lowest channel pin is at the target headroom voltage. Since all LED stacks are connected to the same output voltage, the other channel pins will have a higher voltage, but the regulated current source circuit on each channel will ensure that each channel has the same current. The output voltage will regulate cycle by cycle and it is always referenced to the highest forward voltage string in the architecture.
Dimming Controls
The ISL97672 allows two ways of controlling the LED current, and therefore, the brightness. They are: 1. DC current adjustment 2. PWM chopping of the LED current defined in Step 1. MAXIMUM DC CURRENT SETTING The initial brightness should be set by choosing an appropriate value for RSET. This should be chosen to fix the maximum possible LED current:
401.8 I LEDmax = -------------R SET (EQ. 1)
Current Matching and Current Accuracy
Each channel of the LED current is regulated by the current source circuit, as shown in Figure 19. The LED peak current is set by translating the RSET current to the output with a scaling factor of 401.8/RSET. 9
FN7632.1 November 1, 2010
ISL97672
For example, if the maximum required LED current (ILED(max)) is 20mA, rearranging Equation 1 yields Equation 2:
R SET = 401.8 0.02 = 20.1k (EQ. 2)
input current for systems that have only a low to medium output current requirement. For systems with no master fault protection FET, the inrush current will flow towards COUT when VIN is applied and it is determined by the ramp rate of VIN and the values of COUT and L.
PWM CURRENT CONTROL The ISL97672 employs direct PWM dimming such that the output PWM dimming follows directly with the input PWM signal without modifying the input frequency. The average LED current of each channel can be calculated as Equation 3:
I LED ( ave ) = I LED x PWM (EQ. 3)
Fault Protection and Monitoring
The ISL97672 features extensive protection functions to cover all the perceivable failure conditions. The failure mode of a LED can be either open circuit or as a short. The behavior of an open circuited LED can additionally take the form of either infinite resistance or, for some LEDs, a zener diode, which is integrated into the device in parallel with the now opened LED. For basic LEDs (which do not have built-in zener diodes), an open circuit failure of an LED will only result in the loss of one channel of LEDs without affecting other channels. Similarly, a short circuit condition on a channel that results in that channel being turned off does not affect other channels unless a similar fault is occurring. Due to the lag in boost response to any load change at its output, certain transient events (such as LED current steps or significant step changes in LED duty cycle) can transiently look like LED fault modes. The ISL97672 uses feedback from the LEDs to determine when it is in a stable operating region and prevents apparent faults during these transient events from allowing any of the LED stacks to fault out. See Table 1 for more details. A fault condition that results in an input current that exceeds the devices electrical limits will result in a shutdown of all output channels.
Switching Frequency
The boost switching frequency can be adjusted by a resistor as Equation 4:
( 5 x10 ) f SW = ----------------------R FSW
10
(EQ. 4)
where fSW is the desirable boost switching frequency and RFSW is the setting resistor.
5V Low Dropout Regulator
A 5V LDO regulator is present at the VDC pin to develop the necessary low voltage supply which is used by the chips internal control circuitry. Because VDC is an LDO pin, it requires a bypass capacitor of 1F or more for the regulation. The VDC pin can be used as a coarse reference with few mA sourcing capability.
Inrush Control and Soft-Start
The ISL97672 has separately built-in independent inrush control and soft-start functions. The inrush control function is built around the short circuit protection FET, and is only available in applications which include this device. At start-up, the fault protection FET is turned on slowly due to a 30A pull-down current output from the FAULT pin. This discharges the fault FET's gate-source capacitance, turning on the FET in a controlled fashion. As this happens, the output capacitor is charged slowly through the weakly turned on FET before it becomes fully enhanced. This results in a low inrush current. This current can be further reduced by adding a capacitor (in the 1nF to 5nF range) across the gate source terminals of the FET. Once the chip detects that the fault protection FET is turned on hard, it is assumed that inrush is complete. At this point, the boost regulator will begin to switch and the current in the inductor will ramp-up. The current in the boost power switch is monitored and the switching terminated in any cycle where the current exceeds the current limit. The ISL97672 includes a soft-start feature where this current limit starts at a low value (275mA). This is stepped up to the final 2.2A current limit in seven further steps of 275mA. This is stepped up to the final 2.2A current limit in 7 further steps of 275mA. These steps will happen over at least 8ms, and will be extended at low LED PWM frequencies if the LED duty cycle is low. This allows the output capacitor to be charged to the required value at a low current limit and prevents high
Short Circuit Protection (SCP)
The short circuit detection circuit monitors the voltage on each channel and disables faulty channels which are above approximately 5V (the action taken is described in Table 1).
Open Circuit Protection (OCP)
When one of the LEDs becomes open circuit, it can behave as either an infinite resistance or a gradually increasing finite resistance. The ISL97672 monitors the current in each channel such that any string which reaches the intended output current is considered "good". Should the current subsequently fall below the target, the channel will be considered an "open circuit". Furthermore, should the boost output of the ISL97672 reaches the OVP limit or should the lower over-temperature threshold be reached, all channels which are not "good" will immediately be considered as "open circuit". Detection of an "open circuit" channel will result in a time-out before disabling of the affected channel. This time-out is sped up when the device is above the lower over-temperature threshold in an attempt to prevent the upper over-temperature trip point from being reached. Some users employ some special types of LEDs that have zener diode structure in parallel with the LED for ESD
10
FN7632.1 November 1, 2010
ISL97672
enhancement and enabling open circuit operation. When this type of LED is open circuited, the effect is as if the LED forward voltage has increased but no lighting. Any affected string will not be disabled, unless the failure results in the boost OVP limit being reached, allowing all other LEDs in the string to remain functional. Care should be taken in this case that the boost OVP limit and SCP limit are set properly, so as to make sure that multiple failures on one string do not cause all other good channels to be faulted out. This is due to the increased forward voltage of the faulty channel making all other channels look as if they have LED shorts. See Table 1 for details regarding responses to fault conditions. exceeds the current limit, the internal switch will be turned off. This monitoring happens on a cycle-by-cycle basis in a self protecting way. Additionally, the ISL97672 monitors the voltage at the LX and OVP pins. At start-up, a fixed current is injected out of the LX pins and into the output capacitor. The device will not start-up unless the voltage at LX exceeds 1.2V. The OVP pin is also monitored such that if it rises above and subsequently falls below 20% of the target OVP level, the input protection FET will also be switched off.
Over-Temperature Protection (OTP)
The ISL97672 includes two over-temperature thresholds. The lower threshold is set to +130C. When this threshold is reached, any channel which is outputting current at a level significantly below the regulation target will be treated as "open circuit" and disabled after a timeout period. This time-out period is also reduced to 800s when it is above the lower threshold. The intention of the lower threshold is to allow bad channels to be isolated and disabled before they cause enough power dissipation (as a result of other channels having large voltages across them) to hit the upper temperature threshold. The upper threshold is set to +150C. Each time this is reached, the boost will stop switching and the output current sources will be switched off. Once the device has cooled to approximately +100C, the device will restart with the DC LED current level reduced to 75% of the initial setting. If the dissipation problem persists, subsequent hitting of the limit will cause identical behavior, with the current reduced in steps to 50% and finally 25%. Unless disabled via the EN pin, the device stays in an active state throughout. For the extensive fault protection conditions, please refer to Figure 20 and Table 1 for details.
Overvoltage Protection (OVP)
The integrated OVP circuit monitors the output voltage and keeps the voltage at a safe level. The OVP threshold is set as Equation 5:
OVP = 1.21V x ( R UPPER + R LOWER ) R LOWER (EQ. 5)
These resistors should be large to minimize the power loss. For example, a 1Mk RUPPER and 30k RLOWER sets OVP to 41.2V. Large OVP resistors also allow COUT discharges slowly during the PWM Off time. Parallel capacitors should also be placed across the OVP resistors such that RUPPER/RLOWER = CLOWER/CUPPER. Using a CUPPER value of at least 30pF is recommended. These capacitors reduce the AC impedance of the OVP node, which is important when using high value resistors.
Undervoltage Lockout
If the input voltage falls below the UVLO level of 2.45V, the device will stop switching and be reset. Operation will restart only if the VIN is back in the normal operating range.
Input Overcurrent Protection
During normal switching operation, the current through the internal boost power FET is monitored. If the current
11
FN7632.1 November 1, 2010
ISL97672
VIN LX VOUT
/FLAG DRIVER
FAULT
LX O/P SHORT OVP
IMAX
ILIMIT
LOGIC
FET DRIVER
VSC FAULT FLAG
CH0
CH5
THRM SHDN
REF T2 TEMP SENSOR T1 VSET Q0 VSET
OTP FAULT DETECT LOGIC
Q5
PWM/OC0/SC0 PWM GENERATOR
PWM/OC5/SC5
FIGURE 20. SIMPLIFIED FAULT PROTECTIONS TABLE 1. PROTECTIONS TABLE CASE 1 FAILURE MODE CH0 Short Circuit DETECTION MODE FAILED CHANNEL ACTION GOOD CHANNELS ACTION CH1 through CH5 Normal VOUT REGULATED BY Highest VF of CH1 through CH5
CH0 ON and burns power. Upper Over-Temperature Protection limit (OTP) not triggered and CH0 < 4V
2
CH0 Short Circuit
All channels go off until chip Upper OTP Same as CH0 triggered but VCH0 cooled and then comes back on with current reduced to 76%. < 4V Subsequent OTP triggers will reduce IOUT further. Upper OTP not triggered but CH0 > 4V CH1 disabled after 6 PWM cycle CH1 through CH5 Normal time-out.
Highest VF of CH1 through CH5
3
CH0 Short Circuit
Highest VF of CH1 through CH5 Highest VF of CH1 through CH5 VF of CH0
4
CH0 Open Circuit with infinite resistance CH0 LED Open Circuit but has paralleled Zener
VOUT will ramp to OVP. CH1 will CH1 through CH5 Normal Upper OTP not triggered and CH0 time-out after 6 PWM cycles and < 4V switch off. VOUT will drop to normal level. CH1 remains ON and has Upper OTP not CH1 through CH5 ON, Q1 triggered and CH0 highest VF, thus VOUT increases. through Q5 burn power < 4V
5
12
FN7632.1 November 1, 2010
ISL97672
TABLE 1. PROTECTIONS TABLE (Continued) CASE 6 FAILURE MODE CH0 LED Open Circuit but has paralleled Zener DETECTION MODE Upper OTP triggered but CH0 < 4V FAILED CHANNEL ACTION GOOD CHANNELS ACTION VOUT REGULATED BY VF of CH0
All channels go off until chip Same as CH0 cooled and then comes back on with current reduced to 76%. Subsequent OTP triggers will reduce IOUT further CH0 remains ON and has VOUT increases, then CH-X highest VF, thus VOUT increases. switches OFF after 6 PWM cycles. This is an unwanted shut off and can be prevented by setting OVP at an appropriate level.
7
CH0 LED Open Circuit but has paralleled Zener
Upper OTP not triggered but CHx > 4V
VF of CH0
8
Channel-toChannel VF too high Channel-toChannel VF too high Output LED stack voltage too high VOUT/LX shorted to GND at start-up or VOUT shorted in operation
Lower OTP triggered but CHx < 4V Upper OTP triggered but CHx < 4V VOUT > VOVP
Any channel at below the target current will fault out after 6 PWM Highest VF of CH0 through cycles. CH5 Remaining channels driven with normal current. All channels go off until chip cooled and then comes back on with Highest VF of current reduced to 76%. Subsequent OTP triggers will reduce CH0 through IOUT further CH5 Any channel that is below the target current will time-out after 6 Highest VF of CH0 through PWM cycles, and VOUT will return to the normal regulation CH5 voltage required for other channels. The chip is permanently shutdown 31mS after power-up if VOUT/Lx is shorted to GND.
9
10
11
LX current and timing are monitored. OVP pins monitored for excursions below 20% of OVP threshold.
13
FN7632.1 November 1, 2010
ISL97672
Components Selections
According to the inductor Voltage-Second Balance principle, the change of inductor current during the switching regulator On time is equal to the change of inductor current during the switching regulator Off time. Since the voltage across an inductor is:
V L = L x I L t (EQ. 6)
is usually more suitable for EMI susceptible applications, such as LED backlighting. The peak current can be derived from the fact that the voltage across the inductor during the Off period can be shown as Equation 10:
IL peak = ( V O x I O ) ( 85% x V I ) + 1 2 [ V I x ( V O - V I ) ( L x V O x f S ) ] (EQ. 10)
and IL @ On = IL @ Off, therefore:
( V I - 0 ) L x D x tS = ( VO - VD - VI ) L x ( 1 - D ) x tS (EQ. 7)
where D is the switching duty cycle defined by the turnon time over the switching period. VD is Schottky diode forward voltage that can be neglected for approximation. Rearranging the terms without accounting for VD gives the boost ratio and duty cycle respectively as Equations 8 and 9:
VO VI = 1 ( 1 - D ) D = ( VO - VI ) VO (EQ. 8) (EQ. 9)
The choice of 85% is just an average term for the efficiency approximation. The first term is average current that is inversely proportional to the input voltage. The second term is inductor current change that is inversely proportional to L and fS. As a result, for a given switching frequency and minimum input voltage the system operates, the inductor ISAT must be chosen carefully. At a given inductor size, usually the larger the inductance, the higher the series resistance because of the extra winding of the coil. Thus the higher the inductance, the lower the peak current capability. The ISL97672 current limit may also have to be taken into account.
Output Capacitors
The output capacitor acts to smooth the output voltage and supplies load current directly during the conduction phase of the power switch. Output ripple voltage consists of the discharge of the output capacitor for ILPEAK during FET On and the voltage drop due to flowing through the ESR of the output capacitor. The ripple voltage can be shown as Equation 11:
V CO = ( I O C O x D f S ) + ( ( I O x ESR ) (EQ. 11)
Input Capacitor
Switching regulators require input capacitors to deliver peak charging current and to reduce the impedance of the input supply. This reduces interaction between the regulator and input supply, improving system stability. The high switching frequency of the loop causes almost all ripple current to flow in the input capacitor, which must be rated accordingly. A capacitor with low internal series resistance should be chosen to minimize heating effects and improve system efficiency, such as X5R or X7R ceramic capacitors, which offer small size and a lower value of temperature and voltage coefficient compared to other ceramic capacitors. In boost mode, input current flows continuously into the inductor, with an AC ripple component proportional to the rate of inductor charging only and smaller value input capacitors may be used. It is recommended that an input capacitor of at least 10F be used. Ensure the voltage rating of the input capacitor is suitable to handle the full supply range.
The conservation of charge principle in Equation 9 also brings up a fact that during the boost switch Off period, the output capacitor is charged with the inductor ripple current minus a relatively small output current in boost topology. As a result, the user needs to select an output capacitor with low ESR and with a enough input ripple current capability.
Output Ripple
VCo can be reduced by increasing CO or fS, or using small ESR capacitors. In general, ceramic capacitors are the best choice for output capacitors in small to medium sized LCD backlight applications due to their cost, form factor, and low ESR. A larger output capacitor will also ease the driver response during PWM dimming Off period due to the longer sample and hold effect of the output drooping. The driver does not need to boost harder in the next On period that minimizes transient current. The output capacitor is also needed for compensation, and in general, 2x4.7F/50V ceramic capacitors are suitable for the notebook display backlight applications.
Inductor
The selection of the inductor should be based on its maximum current (ISAT) characteristics, power dissipation (DCR), EMI susceptibility (shielded vs unshielded), and size. Inductor type and value influence many key parameters, including ripple current, current limit, efficiency, transient performance and stability. Its maximum current capability must be adequate to handle the peak current at the worst case condition. If an inductor core is chosen with too low a current rating, saturation in the core will cause the effective inductor value to fall, leading to an increase in peak to average current level, poor efficiency and overheating in the core. The series resistance, DCR, within the inductor causes conduction loss and heat dissipation. A shielded inductor 14
FN7632.1 November 1, 2010
ISL97672
Schottky Diode
A high speed rectifier diode is necessary to prevent excessive voltage overshoot, especially in the boost configuration. Low forward voltage and reverse leakage current will minimize losses, making Schottky diodes the preferred choice. Although the Schottky diode turns on only during the boost switch Off period, it carries the same peak current as the inductor's, and therefore, a suitable current rated Schottky diode must be used.
Compensation
The ISL97672 has two main elements in the system; the Current Mode Boost Regulator and the op amp based multi-channel current sources. The ISL97672 incorporates a transconductance amplifier in its feedback path to allow the user some levels of adjustment on the transient response and better regulation. The ISL97672 uses current mode control architecture, which has a fast current sense loop and a slow voltage feedback loop. The fast current feedback loop does not require any compensation. The slow voltage loop must be compensated for stable operation. The compensation network is a series Rc, Cc1 network from COMP pin to ground and an optional Cc2 capacitor connected to the COMP pin. The Rc sets the high frequency integrator gain for fast transient response and the Cc1 sets the integrator zero to ensure loop stability. For most applications, Rc is in the range of 15k and Cc1 is in the range of 2.2nF. Depends on the PCB layout, a Cc2, in range of 47pF, may be needed to create a pole to cancel the output capacitor ESR's zero effect for stability.
Applications
High Current Applications
Each channel of the ISL97672 can support up to 30mA. For applications that need higher current, multiple channels can be grouped to achieve the desirable current. For example, the cathode of the last LED can be connected to CH0 to CH2; this configuration can be treated as a single string with 90mA current driving capability.
VOUT
CH0 CH1 CH2
FIGURE 21. GROUPING MULTIPLE CHANNELS FOR HIGH CURRENT APPLICATIONS
15
FN7632.1 November 1, 2010
ISL97672
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE 11/1/10 REVISION FN7632.1 CHANGE Corrected part marking in "Ordering Information" on page 3 from "97672" to "7672" In "Thermal Information" on page 4 changed: "Maximum Continuous Junction Temperature . . . . . . +125C To: Absolute Maximum Junction Temperature . . . . . . . . . . . . . . +150C Recommended Max Operating Junction Temperature. . +125C Added "Related Literature*(see page 16)" on page 1. Added "Latch Up (Tested per JESD-78B; Class 2, Level A) 100mA" on page 4 Initial Release.
6/24/10
FN7632.0
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL97672 To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 16
FN7632.1 November 1, 2010
ISL97672
Package Outline Drawing
L20.3x4
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 3/10
3.00 A B
4
0.10 M C A B 0.05 M C 20X 0.25
+0.05 -0.07
16X 0.50 20 1 6 PIN 1 INDEX AREA (C 0.40)
A
6 PIN 1 INDEX AREA 16
17
4.00 2.65
+0.10 -0.15
11 0.15 (4X) 10 7
+0.10 -0.15
6
A
TOP VIEW
VIEW "A-A"
1.65 20x 0.400.10
BOTTOM VIEW
SEE DETAIL "X"
0.9 0.10
0.10 C
C
SEATING PLANE 0.08 C (16 x 0.50) (2.65) (3.80) (20 x 0.25) C 0.2 REF 5
SIDE VIEW
(20 x 0.60) (1.65) (2.80)
0.00 MIN. 0.05 MAX.
DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature.
17
FN7632.1 November 1, 2010

▲Up To Search▲

Price & Availability of ISL97672IRZ

	To Download ISL97672IRZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .